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1 for more information www.linear.com/LTC3330 typical application features description nanopower buck-boost dc/dc with energy harvesting battery life extender the lt c ? 3330 integrates a high voltage energy harvesting power supply plus a dc/ dc converter powered by a primary cell battery to create a single output supply for alternative energy applications. the energy harvesting power sup - ply, consisting of an integrated full-wave bridge rectifier and a high voltage buck converter, harvests energy from piezoelectric, solar, or magnetic sources. the primary cell input powers a buck-boost converter capable of opera - tion down to 1.8 v at its input. either dc/dc converter can deliver energy to a single output. the buck operates when harvested energy is available, reducing the quiescent current draw on the battery to essentially zero, thereby extending the life of the battery. the buck-boost powers v out only when harvested energy goes away. a low noise ldo post regulator and a supercapacitor balancer are also integrated, accommodating a wide range of output storage configurations. voltage and current set - tings for both inputs and outputs are programmable via pin-strapped logic inputs. the LTC3330 is available in a 5 mm 5 mm qfn-32 package . applications n dual input, single output dc/dcs with input prioritizer energy har vesting input: 3.0 v to 19 v buck dc/ dc primary cell input: 1.8 v to 5.5 v buck- boost dc/ dc n zero battery i q when energy harvesting source is available n ultralow quiescent current: 750na at no-load n low noise ldo post regulator n integrated supercapacitor balancer n up to 50ma of output current n programmable dc/dc and ldo output v oltages, buck uvlo, and buck-boost peak input current n integrated low loss full-wave bridge rectifier n input protective shunt: up to 25ma at v in 20v n 5mm 5mm qfn-32 package n energy harvesting n solar powered systems with primary cell backup n wireless hvac sensors and security devices n mobile asset tracking l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. extended battery life with energy harvesting piezo mide v25w 1f 6.3v 4.7f, 6.3v gnd LTC3330 3330 ta01a ac1 v in cap v in2 bat out[2:0] ldo[2:0] ipk[2:0] uv[3:0] ac2 sw swa 22h 22h swb v out ldo_in scap bal ldo_en eh_on pgvout pgldo ldo_out v in3 3v to 19v solar panel 4.7f 6.3v primary cell 1.8v to 5.5v 22f 25v 3 3 3 4 + 1f 6.3v 22f 6.3v 1.2v to 3.3v 50ma 1.8v to 5v 50ma 10mf 2.7v 10mf 2.7v optional 47f 6.3v + ? output voltage 50mv/div ac-coupled eh_on 2v/div ibat 100ma/div 0v 0a 200s/div 3330 ta01b bat = 3.6v v out = 1.8v i load = 50ma active energy harvester reduces battery current to zero 3330fa ltc 3330
2 for more information www.linear.com/LTC3330 pin configuration absolute maximum ratings v in low impedance source .......................... C0.3 to 19v* current-fed, i sw = 0a ........................................ 25ma ac1, ac2 ............................................................. 0 to v in bat, v out , v in3 , ldo_in, scap, pgvout, pgldo, ldo_en ............................................. C0.3 to 6v v in2 .................... C0.3v to [lesser of (v in + 0.3v) or 6v] cap ...................... [higher of C0.3v or (v in C 6v)] to v in ldo_out, ldo[2:0] ................. C0.3v to ldo_in + 0.3v bal ............................................... C0.3v to scap + 0.3v ou t [2:0], ipk [2:0], eh _ on ............. C0. 3 v to [ lesser of (v in 3 + 0.3 v) or 6v] uv[3:0] ............ C0.3v to [lesser of (v in2 + 0.3v) or 6v] i ac1 , i ac2 .............................................................. 50ma i sw , i swa , i swb , i vout .......................................... 350ma i ldo_out ................................................................. 50ma operating junction t emperature range (notes 2, 3) ............................................ C40c to 125c s torage temperature range .................. C65c to 150c *v in has an internal 20v clamp (note 1) 32 33 gnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1bal scap v in2 uv3 uv2 uv1 uv0 ac1 ldo0 ldo1 ldo2 ldo_in ldo_out ipk2 ipk1 ipk0 out2 out1 out0 eh_on pgvout pgldo v in3 ldo_en ac2 v in cap sw v out swb swa bat t jmax = 125c, ja = 44c/w exposed pad ( pin 33) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC3330euh#pbf LTC3330euh#trpbf 3330 32-lead (5mm 5mm) plastic qfn C40c to 85c LTC3330iuh#pbf LTC3330iuh#trpbf 3330 32-lead (5mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3330fa ltc 3330
3 for more information www.linear.com/LTC3330 electrical characteristics symbol parameter conditions min typ max units v in buck input voltage range l 19 v v bat buck-boost input voltage range l 1.8 5.5 v i vin v in quiescent current v in input in uvlo v in input in uvlo buck enabled, sleeping buck enabled, sleeping buck enabled, not sleeping v in = 2.5v, bat = 0v v in = 16v, bat = 0v v in = 4v, bat = 0v v in = 18v, bat = 0v v in = 5v, bat = 0v, i sw1 = 0a (note 4) 450 840 1200 1800 150 700 1400 1800 2500 225 na na na na a i bat bat quiescent current bat input with v in active buck-boost enabled, sleeping buck-boost enabled, not sleeping b at = 1.8 v, v in = 5v bat = 5 v, v in = 0v bat = 5 v , v in = 0v , i swa = i swb = 0 a ( note 4) C10 0 750 200 10 1200 300 na na a i vout v out leakage current v out = 5.0v, out[2:0] = 111, sleeping 100 150 na v inuvlo v in undervoltage lockout thresholds (rising or falling) 3 v level l 2.91 3.00 3.09 v 4v level l 3.88 4.00 4.12 v 5v level l 4.85 5.00 5.15 v 6v level l 5.82 6.00 6.18 v 7v level l 6.79 7.00 7.21 v 8v level l 7.76 8.00 8.24 v 9v level l 8.73 9.00 9.27 v 10v level l 9.70 10.0 10.30 v 11v level l 10.67 11.0 11.33 v 12v level l 11.64 12.0 12.36 v 13v level l 12.61 13.0 13.39 v 14v level l 13.58 14.0 14.42 v 15v level l 14.55 15.0 15.45 v 16v level l 15.52 16.0 16.48 v 17v level l 16.49 17.0 17.51 v 18v level l 17.46 18.0 18.54 v v shunt v in shunt regulator voltage i vin = 1ma l 19.0 20.0 21.0 v i shunt maximum protective shunt current 25 ma internal bridge rectifier loss (|v ac1 C v ac2 | C v in ) i bridge = 10a i bridge = 50ma 700 1350 800 1550 900 1750 mv mv internal bridge rectifier reverse leakage current v reverse = 18v 20 na internal bridge rectifier reverse breakdown voltage i reverse = 1a v shunt 30 v the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 5v, bat = 3.6v, scap = ov, ldo_in = 0v unless otherwise specified. 3330fa ltc 3330
4 for more information www.linear.com/LTC3330 symbol parameter conditions min typ max units v out regulated buck/buck-boost output voltage 1.8v output selected sleep threshold wake-up threshold l l 1.728 1.806 1.794 1.872 v v 2.5 v output selected sleep threshold wake-up threshold l l 2.425 2.508 2.492 2.575 v v 2.8 v output selected sleep threshold wake-up threshold l l 2.716 2.809 2.791 2.884 v v 3.0 v output selected sleep threshold wake-up threshold l l 2.910 3.010 2.990 3.090 v v 3.3 v output selected sleep threshold wake-up threshold l l 3.200 3.311 3.289 3.400 v v 3.6 v output selected sleep threshold wake-up threshold l l 3.492 3.612 3.588 3.708 v v 4.5 v output selected sleep threshold wake-up threshold l l 4.365 4.515 4.485 4.635 v v 5.0 v output selected sleep threshold wake-up threshold l l 4.850 5.017 4.983 5.150 v v pgvout falling threshold as a per centage of v out target (note 5) l 88 92 96 % i peak_buck buck peak switch current 200 250 350 ma i buck available buck output current 100 ma i peak_bb buck-boost peak switch current 250ma target selected 200 250 350 ma 150ma target selected 120 150 210 ma 100ma target selected 80 100 140 ma 50ma target selected 40 50 70 ma 25 ma t arget selected 20 25 35 ma 15ma target selected 12 15 21 ma 10ma target selected 8 10 14 ma 5ma target selected 4 5 7 ma i bb available buck-boost current i peak_bb = 250ma, bat = 1.8v, v out = 3.3v 50 ma r p_buck buck pmos switch on-resistance 1.4 r n_buck buck nmos switch on-resistance 1.2 r p_bb buck-boost pmos input and output switch on-resistance ipk[2:0] = 111 ipk[2:0] = 110 ipk[2:0] = 101 ipk[2:0] = 100 ipk[2:0] = 011 ipk[2:0] = 010 ipk[2:0] = 001 ipk[2:0] = 000 0.7 0.9 1.2 2.1 3.9 6.3 9.2 17.7 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 5v, bat = 3.6v, scap = ov, ldo_in = 0v unless otherwise specified. 3330fa ltc 3330
5 for more information www.linear.com/LTC3330 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 5v, bat = 3.6v, scap = ov, ldo_in = 0v unless otherwise specified. symbol parameter conditions min typ max units r n_bb buck-boost nmos input and output switch on-resistance ipk2 = 1 ipk2 = 0 0.6 3.8 i leak(p) pmos switch leakage buck/buck-boost regulators C20 20 na i leak(n) nmos switch leakage buck/buck-boost regulators C20 20 na maximum buck duty cycle buck/buck-boost regulators l 100 % v ldo_in ldo_in input range l 1.8v 5.5v v i ldo_in ldo_in quiescent current ldo_in = 5.0v, i ldo_out = 0ma 400 600 na i ldo_out ldo_out leakage current ldo_out = 3.3v, ldo[2:0] = 110 100 150 na ldo_out regulated ldo output voltage error as a percentage of target, 100a load l C2.0 C3.0 2.0 3.0 % % ldo line regulation (1.8v to 5.5v) ldo_out = 1.2v, 10ma load 2 mv/v ldo load regulation (10a to 10ma) ldo_in = 5.0v, ldo_out = 3.3v 0.5 mv/ma ldo dropout v oltage ldo_out = 3.3v, 10ma load 50 mv r p_ldo ldo pmos switch on-resistance ldo_in = 3.3v, i ldo_out = 10ma 5 ldo current limit ldo_in = 5.0v 50 ma pgldo rising threshold as a percentage of the 3.3v ldo_out target l 88 92 96 % pgldo falling threshold as a percentage of the 3.3v ldo_out target l 86 90 94 % v scap supercapacitor balancer input range l 2.5 5.5 v i scap supercapacitor balancer quiescent current scap = 5.0v 150 225 na i source supercapacitor balancer source current scap = 5.0v, bal = 2.4v 10 ma i sink supercapacitor balancer sink current scap = 5.0v, bal = 2.6v 10 ma v bal supercapacitor balance point percentage of scap voltage l 49 50 51 % v ih digital input high voltage pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] l 1.2 v v il digital input low voltage pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] l 0.4 v i ih digital input high current pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] 0 10 na i il digital input low current pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] 0 10 na v oh pgvout, pgldo output high voltage eh_on output high voltage b at = 5v, 1a out of pin v in = 6v, 1a out of pin l l 4.0 3.8 v v v ol pgvout, pgldo, eh_on output low voltage bat = 5v, 1a into pin l 0.4 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3330e is tested under pulsed load conditions such that t j t a . the LTC3330e is guaranteed to meet specifications from 0c to 85c. the LTC3330i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient t a and power dissipation pd according to the following formula: t j = t a + (p d ? ja ). note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the pgvout rising threshold is equal to the sleep threshold. see v out specification. 3330fa ltc 3330
6 for more information www.linear.com/LTC3330 typical performance characteristics uvlo threshold vs temperature v shunt vs temperature i vout vs temperature total bridge rectifier drop vs bridge current bridge leakage vs temperature bridge frequency response i vin in uvlo vs v in i vin in sleep vs v in i b at in sleep vs b at v in (v) 0 i vin (na) 2200 2000 1600 1200 1800 1400 1000 800 600 400 200 0 96 15 3330 g01 18 3 12 125c 85c 25c ?40c bat (v) 1.5 i bat (na) 2100 1800 1500 1200 900 600 300 0 3.5 4.5 3330 g03 5.5 2.5 85c 25c ?40c 125c temperature (c) ?50 percentage of target setting (%) 103 102 101 100 99 98 97 0 25 50 75 100 3330 g04 125 ?25 applies to each uvlo setting bridge current (a) v bridge (mv) 1800 1600 1400 1200 1000 800 600 400 200 0 3330 g07 1 10 100m 10m 100 ?40c 25c 85c 125c |v ac1 ? v ac2 | ? v in temperature (c) ?50 v shunt (v) 21.0 20.8 20.6 20.4 20.2 20.0 19.8 19.6 19.2 19.4 19.0 0 25 50 75 100 3330 g05 125 ?25 i shunt = 1ma i shunt = 25ma temperature (c) ?50 i vout (na) 150 140 130 120 110 100 90 80 60 70 50 0 25 50 75 100 3330 g05 125 ?25 v out in regulation, sleeping frequency (hz) v in (v) 3330 g09 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 100 100m10m1m 10k1k 100k 4.8v p-p applied to ac1/ac2 input measured in uvlo t a = 25c, unless otherwise noted. temperature (c) ?55 bridge leakage (na) 20 18 14 10 16 12 6 8 4 2 0 8035 125 3330 g08 170 ?10 v in = 18v, leakage at ac1 or ac2 v in (v) i vin (na) 6000 5000 4000 3000 2000 1000 0 96 15 3330 g02 18 3 12 125c ?40c 85c 25c 3330fa ltc 3330
7 for more information www.linear.com/LTC3330 typical performance characteristics 3v output vs temperature 3.3v output vs temperature 3.6v output vs temperature 4.5v output vs temperature 5v output vs temperature r ds(on) of buck-boost pmos/nmos vs temperature, 250ma setting 1.8v output vs temperature 2.5v output vs temperature 2.8v output vs temperature temperature (c) ?50 v out (v) 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70 1.68 1.66 1.64 0 25 50 75 100 3330 g10 125 ?25 sleep threshold pgood falling wake-up threshold temperature (c) ?50 v out (v) 2.55 2.50 2.45 2.40 2.35 2.30 2.25 0 25 50 75 100 3330 g11 125 ?25 sleep threshold pgood falling wake-up threshold temperature (c) ?50 v out (v) 2.85 2.80 2.75 2.70 2.65 2.60 2.55 0 25 50 75 100 3330 g12 125 ?25 sleep threshold pgood falling wake-up threshold temperature (c) ?50 v out (v) 3.05 3.00 2.95 2.90 2.85 2.80 2.75 2.70 0 25 50 75 100 3330 g13 125 ?25 sleep threshold pgood falling wake-up threshold temperature (c) ?50 v out (v) 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.00 0 25 50 75 100 3330 g14 125 ?25 sleep threshold pgood falling wake-up threshold temperature (c) ?50 v out (v) 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.30 3.25 0 25 50 75 100 3330 g15 125 ?25 sleep threshold pgood falling wake-up threshold temperature (c) ?50 v out (v) 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 0 25 50 75 100 3330 g16 125 ?25 sleep threshold pgood falling wake-up threshold temperature (c) ?50 v out (v) 5.10 5.00 4.90 4.80 4.70 4.60 4.50 0 25 50 75 100 3330 g17 125 ?25 sleep threshold pgood falling wake-up threshold t a = 25c, unless otherwise noted. temperature (c) ?50 r ds(on) () 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 25 50 75 100 3330 g18 125 ?25 pmos, bat = 1.8v pmos, bat = 5v nmos, bat = 1.8v nmos, bat = 5v 3330fa ltc 3330
8 for more information www.linear.com/LTC3330 typical performance characteristics buck-boost load regulation, 3.3v buck-boost line regulation, 3.3v buck-boost switching waveforms buck load regulation, 3.3v buck line regulation, 3.3v buck switching waveforms r ds(on) of buck-boost pmos/nmos vs temperature, 5ma setting i peak_bb vs temperature, 250ma setting i peak_bb vs temperature, 5ma setting t a = 25c, unless otherwise noted. temperature (c) ?50 r ds(on) () 55 50 45 40 35 30 25 20 15 10 5 0 0 25 50 75 100 3330 g19 125 ?25 pmos, bat = 1.8v nmos, bat = 1.8v pmos, bat = 5v nmos, bat = 5v temperature (c) ?50 i peak_bb (ma) 300 290 280 270 260 230 220 210 250 200 240 0 25 50 75 100 3330 g20 125 ?25 bat = 3.6v temperature (c) ?50 i peak_bb (ma) 6.0 5.8 5.6 5.4 5.2 4.6 4.4 4.2 5.0 4.0 4.8 0 25 50 75 100 3330 g21 125 ?25 bat = 3.6v i load (a) v out (v) 3.400 3.375 3.350 3.325 3.300 3.275 3.225 3.250 3.200 3330 g22 1 10 10m 100m 1m 100 bat = 5v bat = 1.8v c out = 100f l = 22h ipk[2:0] = 111 bat (v) 1.8 v out (v) 3.400 3.375 3.350 3.325 3.300 3.275 3.250 3.225 3.200 2.6 3.0 3.4 3.8 4.2 4.6 3330 g23 5 2.2 load = 1ma load = 100ma c out = 100f l = 22h ipk[2:0] = 111 bat = 1.8v, v out = 3.3v i load = 10ma l = 22h, c out = 100f swa voltage 2v/div swb voltage 2v/div output voltage 50mv/div ac-coupled inductor current 200ma/div 3330 g24 20s/div 0v 0v 0ma i load (a) v out (v) 3.400 3.375 3.350 3.325 3.300 3.275 3.225 3.250 3.200 3330 g25 1 10 10m 100m 1m 100 v in = 4v c out = 100f l = 22h v in (v) 4 v out (v) 3.400 3.375 3.350 3.325 3.300 3.275 3.250 3.225 3.200 8 10 12 14 16 3330 g26 18 6 load = 1ma load = 100ma c out = 100f l = 22h v in = 18v, v out = 3.3v i load = 10ma l = 22h, c out = 100f 0v sw voltage 10v/div output voltage 50mv/div ac-coupled inductor current 200ma/div 0ma 3330 g27 8s/div 3330fa ltc 3330
9 for more information www.linear.com/LTC3330 typical performance characteristics buck-boost load step response buck load step response prioritizer buck-boost to buck transition buck efficiency vs i load buck efficiency vs v in for i load = 100ma, l = 22h i peak_buck vs temperature r ds(on) of buck pmos/nmos vs temperature prioritzer buck to buck-boost transition buck efficiency vs v in for i load = 100ma, l = 100h temperature (c) ?50 i peak_buck (ma) 300 290 280 270 260 250 240 230 220 200 210 0 25 50 75 100 3330 g28 125 ?25 v in = 5v temperature (c) ?50 r ds(on) () 2.0 1.8 1.6 1.4 1.2 0.8 1.0 0 25 50 75 100 3330 g29 125 ?25 v in = 5v pmos nmos t a = 25c, unless otherwise noted. bat = 3v, v out = 3.3v c out = 100f, l = 22f load step from 1ma to 50ma output voltage 20mv/div ac-coupled load current 25ma/div 1ma 3330 g31 2ms/div v in = 18v, v out = 3.3v c out = 100f, l = 22f load step from 1ma to 50ma output voltage 20mv/div ac-coupled load current 25ma/div 1ma 3330 g32 2ms/div v in transitions 17v to 18v, uv[3:0] = 1110 bat = 4.1v, v out = 3.3v i load = 50ma, c out = 100f, l buck = 22h, l buck-boost = 22h 0v 0ma eh_on 5v/div buck inductor current 200ma/div output voltage 50mv/div dc-coupled, offset = 3.3v buck-boost inductor current 200ma/div 3330 g33 100s/div 0ma v in transitions 18v to 17v, uv[3:0] = 1110 bat = 4.1v, v out = 3.3v i load = 50ma, c out = 100f, l buck = 22h, l buck-boost = 22h 0v 0ma eh_on 5v/div buck inductor current 200ma/div output voltage 50mv/div dc-coupled, offset = 3.3v buck-boost inductor current 200ma/div 0ma 3330 g30 100s/div i load (a) efficiency (%) 3330 g34 100 90 60 80 70 40 50 20 10 30 0 1 10 10m 100m 1m 100 1.8v 2.5v 3.3v 5v v in = 6v, l = 22h, dcr = 0.19 v out setting v in (v) efficiency (%) 3330 g35 100 90 95 85 80 75 4 6 108 12 14 16 18 1.8v 2.5v 2.8v 3v 3.3v 3.6v 4.5v 5v dcr = 0.19 v out setting v in (v) efficiency (%) 3330 g36 100 90 95 85 80 75 4 6 108 12 14 16 18 dcr = 0.45 1.8v 2.5v 2.8v 3v 3.3v 3.6v 4.5v 5v v out setting 3330fa ltc 3330
10 for more information www.linear.com/LTC3330 typical performance characteristics buck-boost efficiency vs b at for v out = 1.8v, 250ma i peak setting buck-boost efficiency vs b at for v out = 3.3v, 250ma i peak setting buck-boost efficiency vs b at for v out = 5v, 250ma i peak setting buck-boost efficiency vs b at for v out = 1.8v, 5ma i peak setting buck-boost efficiency vs b at for v out = 3.3v, 5ma i peak setting buck-boost efficiency vs b at for v out = 5v, 5ma i peak setting buck efficiency vs v in , for v in = 3.3v buck-boost efficiency vs i load , 250ma setting buck-boost efficiency vs i load , 5ma i peak setting t a = 25c, unless otherwise noted. bat (v) efficiency (%) 3330 g45 100 80 70 60 90 50 40 1.8 2.2 32.6 3.4 3.8 4.2 54.6 l = 1000h, dcr = 5.1 50ma 50a 10a 100a 20a 5a load current bat (v) efficiency (%) 3330 g44 100 80 70 60 90 50 40 1.8 2.2 32.6 3.4 3.8 4.2 54.6 l = 1000h, dcr = 5.1 50ma 50a 10a 100a 20a 5a load current bat (v) efficiency (%) 3330 g40 100 80 70 60 90 50 40 1.8 2.2 32.6 3.4 3.8 4.2 54.6 l = 22h, dcr = 0.36 50ma 50a 10a 100a 20a 5a load current bat (v) efficiency (%) 3330 g41 100 80 70 60 90 50 40 1.8 2.2 32.6 3.4 3.8 4.2 54.6 l = 22h, dcr = 0.36 50ma 50a 10a 100a 20a 5a load current bat (v) efficiency (%) 3330 g42 100 80 70 60 90 50 40 1.8 2.2 32.6 3.4 3.8 4.2 54.6 l = 22h, dcr = 0.36 50ma 50a 10a 100a 20a 5a load current v in (v) efficiency (%) 3330 g37 100 80 70 60 90 50 40 30 20 10 0 4 6 108 12 14 16 18 100ma 100a 50a 30a 20a 10a 5a l = 22h, dcr = 0.19 load current bat (v) efficiency (%) 3330 g43 100 80 70 60 90 50 40 1.8 2.2 32.6 3.4 3.8 4.2 54.6 l = 1000h, dcr = 5.1 50ma 50a 10a 100a 20a 5a load current i load (a) efficiency (%) 3330 g38 100 90 80 70 60 50 40 30 20 10 0 1 10 10m 1m 100 bat = 3.6v l = 22h dcr = 0.36 1.8v 2.5v 3.5v 5v v out setting i load (a) efficiency (%) 3330 g39 100 90 80 70 60 50 40 30 20 10 0 1 10 1m 100 bat = 3.6v l = 1000h dcr = 5.1 1.8v 2.5v 3.5v 5v v out setting 3330fa ltc 3330
11 for more information www.linear.com/LTC3330 typical performance characteristics ldo load regulation, 1.2v ldo line regulation, 1.2v ldo start-up ldo load regulation, 3.3v ldo line regulation, 3.3v i ldo_in vs ldo_in ldo_out vs temperature, ldo_out = 3.3v ldo load step ldo_in (v) 1.5 i ldo_in (na) 900 800 700 600 500 400 300 200 100 0 2.5 3.5 4.5 3330 g46 5.5 125c 85c 25c ?40c t a = 25c, unless otherwise noted. i load (a) ldo_out (v) 1.224 1.218 1.212 1.206 1.200 1.194 1.182 1.188 1.176 3330 g47 1 10 10m 100m 1m 100 ldo_in = 5v ldo_in = 1.8v ldo_in (v) 1.8 ldo_out (v) 1.224 1.218 1.212 1.206 1.200 1.194 1.188 1.182 1.176 2.6 3 3.4 3.8 4.2 4.6 3330 g48 5 2.2 load = 100a load = 10ma temperature (c) ?50 ldo_out (v) 3.36 3.34 3.32 3.30 3.28 3.24 3.26 0 25 50 75 100 3330 g49 125 ?25 ldo_in = 3.6v, 100a load i load (a) ldo_out (v) 3.36 3.34 3.32 3.30 3.26 3.28 3.24 3330 g50 1 10 10m 100m 1m 100 ldo_in = 5v ldo_in = 3.6v ldo_in (v) 3.4 ldo_out (v) 3.36 3.34 3.32 3.30 3.28 3.26 3.24 3.8 4 4.2 4.4 4.6 4.8 3330 g51 5 3.6 load = 100a load = 10ma ldo_in = 5v, ldo[2:0] = 110 c ldo_out = 22f ldo_out voltage 1v/div ldo_en voltage 5v/div 3330 g52 2ms/div 0v 0v ldo_in = 5v, ldo_out = 3.3v c ldo_out = 33f load step between 1ma and 50ma ldo_out voltage ac-coupled 20mv/div load current 50ma/div 3330 g53 2ms/div 0ma 3330fa ltc 3330
12 for more information www.linear.com/LTC3330 pin functions bal (pin 1): supercapacitor balance point. the common node of a stack of two supercapacitors is connected to bal. a source/sink balancing current of up to 10 ma is available. tie bal along with scap to gnd to disable the balancer and its associated quiescent current. scap ( pin 2): supply and input for supercapacitor balancer. tie the top of a 2- capacitor stack to scap and the middle of the stack to bal to activate balancing. tie scap along with bal to gnd to disable the balancer and its associated quiescent current. v in2 (pin 3): internal low voltage rail to serve as gate drive for buck nmos switch. connect a 4.7f ( or larger) capacitor from v in2 to gnd. this pin is not intended for use as an external system rail. uv3, uv2, uv1, uv 0 (pins 4, 5, 6, 7): uvlo select bits for the buck switching regulator. tie high to v in2 or low to gnd to select the desired uvlo rising and falling thresholds (see table 4). the uvlo falling threshold must be greater than the selected v out regulation level. do not float. ac1 (pin 8): input connection for piezoelectric element, other ac source, or current limited dc source ( used in conjunction with ac2 for differential ac inputs). ac2 (pin 9): input connection for piezoelectric element, other ac source, or current limited dc source ( used in conjunction with ac1 for differential ac inputs). i scap vs scap supercapacitor balancer source/ sink current typical performance characteristics t a = 25c, unless otherwise noted. scap (v) 2 i scap (na) 250 200 150 100 50 0 3 4 4.5 5 3.5 3330 g55 5.5 2.5 85c 125c 25c ?40c v bal /v scap (%) 0 balancer source/sink current (ma) 50 40 30 20 10 0 ?10 ?20 20 30 50 60 70 80 90 40 3330 g56 100 10 scap = 5v scap = 2.5v v in (pin 10): rectified input voltage. a capacitor on this pin serves as an energy reservoir and input supply for the buck regulator. the v in voltage is internally clamped to a maximum of 20v (typical). cap (pin 11): internal rail referenced to v in to serve as gate drive for buck pmos switch. connect a 1f (or larger) capacitor between cap and v in . this pin is not intended for use as an external system rail. sw (pin 12): switch node for the buck switching regula- tor. connect a 22 h or greater external inductor between this node and v out . v out (pin 13): regulated output voltage derived from the buck or buck-boost switching regulator. swb (pin 14): switch node for the buck-boost switching regulator. connect an external inductor ( value in table 3) between this node and swa . swa (pin 15): switch node for the buck-boost switching regulator. connect an external inductor ( value in table 3) between this node and swb. b at (pin 16): battery input. bat serves as the input to the buck-boost switching regulator. r ds(on) of ldo pmos vs temperature temperature (c) ?50 r ds(on) () 12 11 10 9 8 5 4 7 3 6 0 25 50 75 100 3330 g54 125 ?25 ldo_in = 1.8v ldo_in = 2.5v ldo_in = 3.3v ldo_in = 5v 3330fa ltc 3330
13 for more information www.linear.com/LTC3330 ipk0, ipk1, ipk 2 ( pins 17, 18, 19): i peak_bb select bits for the buck-boost switching regulator. tie high to v in3 or low to gnd to select the desired i peak_bb ( see table 3). do not float. ldo _out (pin 20): regulated ldo output. this output can be used as a quiet supply. one of the eight settings provides for a current limited switched output where ldo_out = ldo_in. ldo_in (pin 21): input voltage for the ldo regulator. ldo2, ldo1, ldo 0 (pins 22, 23, 24): ldo voltage select bits. tie high to ldo_in or low to gnd to select the desired ldo_out voltage (see table 2). do not float. ldo_en (pin 25): ldo enable input. active high input with logic levels referenced to ldo_in. do not float. v in3 (pin 26): internal low voltage rail used by the pri- oritizer. logic high reference for ipk[2:0] and out[2:0]. connect a 1f ( or larger) capacitor from v in3 to gnd. this pin is not intended for use as an external system rail. pgldo (pin 27): power good output for ldo_out. logic level output referenced to an internal maximum rail ( see operation). pgldo transitioning high indicates 92% ( typical) regulation has been reached on ldo_out. pgldo remains high until ldo_out falls to 90% (typical) of the programmed regulation point. pin functions pgvout (pin 28): power good output for v out . logic level output referenced to an internal maximum rail (see operation). pgvout transitioning high indicates regula - tion has been reached on v out (v out = sleep rising). pgvout remains high until v out falls to 92% (typical) of the programmed regulation point. eh_on (pin 29): switcher status. logic level output referenced to v in3 . eh _ on is high when the buck switching regulator is in use. it is pulled low when the buck-boost switching regulator is in use. out0, out1, out 2 (pins 30, 31, 32): v out voltage select bits. tie high to v in3 or low to gnd to select the desired v out (see table 1). do not float. gnd ( exposed pad pin 33): ground. the exposed pad must be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the LTC3330. 3330fa ltc 3330
14 for more information www.linear.com/LTC3330 block diagram 3330 bd bandgap reference internal rail generation prioritzer uvlo uvlo_set sleep v in v ref ac1 20v 10 8 ac2 bat 9 16 eh_on sleep ilim_set v ref v in2 v in3 v max v max bat v out pgvout pgldo 29 28 27 ? + ? + sleep 0.9*v ref v ref ? + ? + 0.925*v ref v in2 ldo_in v in3 v in3 cap 11 sw v in2 gnd 33 swa swb ldo_in v out 15 14 13 21 ldo_out scap bal 20 2 1 v in3 26 buck-boost control ilim_set uvlo_set 12 3 3 3 32, 31, 30 22, 23, 24 4 4, 5, 6, 7 uv[3:0] 3 19, 18, 17 ipk[2:0] out[2:0] ldo[2:0] buck control ldo_en 25 ? + 3330fa ltc 3330
15 for more information www.linear.com/LTC3330 operation modes of operation the following four tables detail all programmable settings on the LTC3330. table 1. output voltage selection out2 out1 out0 v out 0 0 0 1.8v 0 0 1 2.5v 0 1 0 2.8v 0 1 1 3.0v 1 0 0 3.3v 1 0 1 3.6v 1 1 0 4.5v 1 1 1 5.0v table 2. ldo voltage selection ldo2 ldo1 ldo0 ldo_out 0 0 0 1.2v 0 0 1 1.5v 0 1 0 1.8v 0 1 1 2.0v 1 0 0 2.5v 1 0 1 3.0v 1 1 0 3.3v 1 1 1 = ldo_in table 3. i peak_bb selection ipk2 ipk1 ipk0 i lim l min 0 0 0 5ma 1000h 0 0 1 10ma 470h 0 1 0 15ma 330h 0 1 1 25ma 220h 1 0 0 50ma 100h 1 0 1 100ma 47h 1 1 0 150ma 33h 1 1 1 250ma 22h table 4. v in uvlo threshold selection uv3 uv2 uv1 uv0 uvlo rising uvlo falling 0 0 0 0 4v 3v 0 0 0 1 5v 4v 0 0 1 0 6v 5v 0 0 1 1 7v 6v 0 1 0 0 8v 7v 0 1 0 1 8v 5v 0 1 1 0 10v 9v 0 1 1 1 10v 5v 1 0 0 0 12v 11v 1 0 0 1 12v 5v 1 0 1 0 14v 13v 1 0 1 1 14v 5v 1 1 0 0 16v 15v 1 1 0 1 16v 5v 1 1 1 0 18v 17v 1 1 1 1 18v 5v 3330fa ltc 3330
16 for more information www.linear.com/LTC3330 overview the LTC3330 combines a buck switching regulator and a buck-boost switching regulator to produce an energy harvesting solution with battery backup. the converters are controlled by a prioritizer that selects which converter to use based on the availability of a battery and/ or harvestable energy. if harvested energy is available the buck regula - tor is active and the buck-boost is off. with an optional ldo and supercapacitor balancer and an array of different configurations the LTC3330 suits many applications. buck converter the synchronous buck converter is an ultralow quiescent current power supply tailored to energy harvesting applica - tions. it is designed to interface directly to a piezoelectric or alternative a/c power source, rectify the input voltage, and store harvested energy on an external capacitor while maintaining a regulated output voltage. it can also bleed off any excess input power via an internal protective shunt regulator. internal bridge rectifier an internal full-wave bridge rectifier accessible via the dif - ferential ac 1 and ac2 inputs rectifies ac sources such as those from a piezoelectric element. the rectified output is stored on a capacitor at the v in pin and can be used as an energy reservoir for the buck converter . the bridge rectifier has a total drop of about 800 mv at typical piezo-generated currents (~10 a), but is capable of carrying up to 50ma. either side of the bridge can be operated independently as a single-ended ac or dc input. buck undervoltage lockout (uvlo) when the voltage on v in rises above the uvlo rising threshold the buck converter is enabled and charge is transferred from the input capacitor to the output capaci - tor. when the input capacitor voltage is depleted below the uvlo falling threshold the buck converter is disabled. these thresholds can be set according to table 4 which offers uvlo rising thresholds from 4 v to 18 v with large or small hysteresis windows. this allows for program - ming of the uvlo window near the peak power point of operation figure 1. ideal v in , v in2 and cap relationship the input source. extremely low quiescent current (450na typical) in uvlo allows energy to accumulate on the input capacitor in situations where energy must be harvested from low power sources. internal rail generation (cap, v in2 , v in3 ) tw o internal rails, cap and v in2 , are generated from v in and are used to drive the high side pmos and low side nmos of the buck converter, respectively. additionally the v in2 rail serves as logic high for the uvlo threshold select bits uv[3:0]. the v in2 rail is regulated at 4.8 v above gnd while the cap rail is regulated at 4.8 v below v in . these are not intended to be used as external rails. bypass capaci- tors are connected to the cap and v in2 pins to serve as energy reservoirs for driving the buck switches. when v in is below 4.8 v, v in2 is equal to v in and cap is held at gnd. figure 1 shows the ideal v in , v in2 and cap relationship. v in (v) 0 voltage (v) 18 12 14 16 10 2 4 8 6 0 10 5 3330 f01 15 v in v in2 cap v in3 is an internal rail used by the buck and the buck-boost. when the LTC3330 runs the buck v in3 will be a schottky diode drop below v in2 . when it runs the buck-boost v in3 is equal to bat . buck operation the buck regulator uses a hysteretic voltage algorithm to control the output through internal feedback from the v out sense pin. the buck converter charges an output capacitor through an inductor to a value slightly higher than the regulation point. it does this by ramping the inductor current up to i peak_buck through an internal 3330fa ltc 3330
17 for more information www.linear.com/LTC3330 operation pmos switch and then ramping it down to 0 ma through an internal nmos switch. this efficiently delivers energy to the output capacitor. the ramp rate is determined by v in , v out , and the inductor value. when the buck brings the output voltage into regulation the converter enters a low quiescent current sleep state that monitors the output voltage with a sleep comparator. during this operating mode load current is provided by the output capacitor. when the output voltage falls below the regulation point the buck regulator wakes up and the cycle repeats. this hysteretic method of providing a regulated output reduces losses associated with fet switching and maintains an output at light loads. the buck delivers a minimum of 100ma of average load current when it is switching. v out can be set from 1.8 v to 5 v via the output voltage select bits, out[2:0] (see table 1). when the sleep comparator senses that the output has reached the sleep threshold the buck converter may be in the middle of a cycle with current still flowing through the inductor. normally both synchronous switches would turn off and the current in the inductor would freewheel to zero through the nmos body diode , but the nmos switch is kept on to prevent the conduction loss that would occur in the diode if the nmos were off. if the pmos is on when the sleep comparator trips the nmos will turn on immediately in order to ramp down the current. if the nmos is on it will be kept on until the current reaches zero. though the quiescent current when the buck is switching is much greater than the sleep quiescent current, it is still a small percentage of the average inductor current which results in high efficiency over most load conditions. the buck operates only when sufficient energy has been ac - cumulated in the input capacitor and the length of time the converter needs to transfer energy to the output is much less than the time it takes to accumulate energy. thus, the buck operating quiescent current is averaged over a long period of time so that the total average quiescent current is low. this feature accommodates sources that harvest small amounts of ambient energy. buck-boost converter the buck- boost uses the same hysteretic voltage algorithm as the buck to control the output, v out , with the same sleep comparator. the buck-boost has three modes of operation: buck, buck-boost, and boost. an internal mode comparator determines the mode of operation based on bat and v out . figure 2 shows the four internal switches of the buck-boost converter. in each mode the inductor current is ramped up to i peak_bb , which is programmable via the ipk[2:0] bits and ranges from 5 ma to 250 ma (see table 3). in buck mode m4 is always on and m3 is always off. the inductor current is ramped up through m1 to i peak_bb and down to 0 ma through m2. in boost mode m1 is always on and m2 is always off. the inductor current is ramped up to i peak_bb when m3 is on and is ramped down to 0ma when m4 is on as v out is greater than bat in boost mode. buck-boost mode is very similar to boost mode in that m1 is always on and m2 is always off. if bat is less than v out the inductor current is ramped up to i peak_bb through m3. when m4 turns on the current in the inductor will start to ramp down. however, because bat is close to v out and m1 and m4 have finite on-resistance the current ramp will exhibit a slow exponential decay, lowering the average current delivered to v out . for this reason the lower current threshold is set to i peak_bb /2 in buck-boost mode to maintain high average current to the load. if bat is greater than v out in buck-boost mode the inductor current still ramps up to i peak_bb and down to i peak_bb /2. it can still ramp down if bat is greater than v out because the final value of the current in the inductor would be (v in C v out )/ (r on1 + r on4 ). if bat is exactly i peak_bb / 2?(r on1 + r on4 ) above v out the inductor current will figure 2: buck-boost power switches 3330 f02 swa swb m1 bat m4 v out m3 m2 3330fa ltc 3330
18 for more information www.linear.com/LTC3330 not reach the i peak_bb /2 threshold and switches m1 and m4 will stay on all the time. for higher bat voltages the mode comparator will switch the converter to buck mode. m1 and m4 will remain on for bat voltages up to v out + i peak_bb ?(r on1 + r on4 ). at this point the current in the inductor is equal to i peak_bb and the i peak_bb compara- tor will trip turning off m1 and turning on m2 causing the inductor current to ramp down to izero, completing the transition from buck-boost mode to buck mode. v out power good a power good comparator is provided for the v out output. it transitions high the first time the LTC3330 goes to sleep, indicating that v out has reached regulation. it transitions low when v out falls to 92% ( typical) of its value at regula- tion. the pgvout output is referenced to an internal rail that is generated to be the highest of v in2 , bat , and v out less a schottky diode drop. prioritizer the input prioritizer on the LTC3330 decides whether to use the energy harvesting input or the battery input to power v out . if a battery is powering the buck-boost converter and harvested energy causes a uvlo rising transition on v in , the prioritizer will shut off the buck-boost and turn on the buck, orchestrating a smooth transition that maintains regulation of v out . when harvestable energy disappears, the prioritizer will first poll the battery voltage. if the battery voltage is above 1.8 v the prioritizer will switch back to the buck-boost while maintaining regulation. if the battery voltage is below 1.8 v the buck-boost is not enabled and v out cannot be supported until harvestable energy is again available. if either bat or v in is grounded, the prioritizer allows the other input to run if its input is high enough for operation. the specified quiescent current in uvlo is valid upon start-up of the v in input and when the battery has taken over regulation of the output. if the battery is less than 1.8v when uvlo is entered and the prioritizer does not enable the buck-boost several hundred nanoamperes of additional quiescent current will appear on v in . when the prioritizer selects the v in input the current on the bat input drops to zero. however, if the voltage on bat is higher than v in2 , a fraction of the v in quiescent current will appear on bat due to internal level shifting. this only affects a small range of battery voltages and uvlo settings. a digital output, eh_on, is low when the prioritizer has selected the bat input and is high when the prioritizer has selected the v in input. the eh_on output is referenced to v in3 . low drop out regulator an integrated low drop out regulator ( ldo) is available with its own input, ldo_in. it will regulate ldo_out to seven different output voltages based on the ldo[2:0] pins. an eighth mode is provided to turn the ldo into a current- limited switch in which the pmos is always on. ldo_en enables the ldo when high and when low eliminates all quiescent current on ldo_in. the ldo is designed to provide 50 ma over a range of ldo_in and ldo_out combinations. a current limit set above 50 ma is available to dial back the current if the output is grounded or the load demands more than 50 ma. the ldo also features a 1ms soft-start for smooth output start-up. a power good signal on the pgldo pin indicates when the voltage at ldo_out rises above 92% ( typical) of its final value, or after tripped, when the ldo_out falls below 90% of that value. the pgldo output is referenced to an internal rail that is generated to be the highest of v in2 , bat , and v out less a schottky diode drop. supercapacitor balancer an integrated supercapacitor balancer with 150 na of quiescent current is available to balance a stack of two supercapacitors. typically the input, scap, will tie to v out to allow for increased energy storage at v out with supercapacitors. the bal pin is tied to the middle of the stack and can source and sink 10 ma to regulate the bal pins voltage to half that of the scap pins voltage. to disable the balancer and its associated quiescent current the scap and bal pins can be tied to ground. operation 3330fa ltc 3330
19 for more information www.linear.com/LTC3330 applications the LTC3330 allows for energy harvesting from a variety of alternative energy sources in order to extend the life of a battery powered wireless sensor system. the extremely low quiescent current of the LTC3330 facilitates harvesting from sources generating only microamps of current. the onboard bridge rectifier is suitable for ac piezoelectric or electromagnetic sources as well as providing reverse protection for dc sources such as solar and thermoelec - tric generators . the LTC3330 powers the v out output continuously by seamlessly switching between the energy harvesting and battery inputs. when harvestable energy is available, it is transferred through the bridge rectifier where it accumulates on the v in capacitor. a low quiescent current uvlo mode allows the voltage on the capacitor to increase towards a pro- grammed uvlo rising threshold. when the voltage rises to this level, the buck converter turns on and transfers energy to v out . as energy is transferred the voltage at v in may decrease to the uvlo falling threshold. if this happens, the buck converter turns off and the buck-boost then turns on to service the load from the battery input while more energy is harvested. when the buck is running the quiescent current on the bat pin is essentially zero. the LTC3330 is well suited to wireless systems which consume low average power but occasionally need a higher concentrated burst of power to accomplish a task. if these bursts occur with a low duty cycle such that the total energy needed for a burst can be accumulated between bursts then the output can be maintained entirely by the harvester. if the bursts need to happen more frequently or if harvestable energy goes away the battery will be used. piezo energy harvesting ambient vibrational energy can be harvested with a piezo - electric transducer which produces a voltage and current in response to strain. common piezoelectric elements are pzt ( lead zirconate titanate) ceramics, pvdf (polyvinyli - dene fluoride) polymers, or other composites. ceramic piezoelectric elements exhibit a piezoelectric effect when the crystal structure of the ceramic is compressed and internal dipole movement produces a voltage. polymer elements comprised of long-chain molecules produce a voltage when flexed as molecules repel each other. ceram - ics are often used under direct pressure while a polymer is commonly used as a cantilevered beam. a wide range of piezoelectric elements are available and produce a variety of open- circuit voltages and short - circuit currents. typically the open- circuit voltage and short- circuit currents increase with available vibrational energy as shown in figure 3. piezoelectric elements can be placed in series or in parallel to achieve desired open-circuit voltages. piezos produce the most power when they operate at approximately half the open circuit voltage for a given vibration level. the uvlo window can be programmed to straddle this voltage so that the piezo operates near the peak power point. in addition to the normal configuration of connecting the piezo across the ac1 and ac2 inputs, a piezo can be connected from either ac1 or ac2 to ground. the resulting configuration is a voltage doubler as seen in figure 4 where the intrinsic capacitance of the piezo is used as the doubling capacitor. figure 3. typical piezoelectric load lines for piezo systems t220-a4-503x piezo current (a) 0 piezo voltage (v) 12 9 6 3 0 20 10 3330 f03 30 increasing vibration energy 3330fa ltc 3330
20 for more information www.linear.com/LTC3330 applications a second piezo may be connected from ac2 to ground. this may be of use if the second piezo is mechanically tuned to a different resonant frequency present in the system than the first piezo. of the two piezos the one operating at the higher open circuit voltage will win over the other piezo and its doubled voltage will appear on the v in capacitor. to achieve maximum power transfer from the piezo with the doubler the uvlo window should be set to the open circuit voltage of the piezo. piezoelectric elements are available from the manufactur - ers listed in table 5. table 5. piezoelectric element manufacturers advanced cerametrics www.advancedcerametrics.com piezo systems www.piezo.com measurement specialties www.meas-spec.com pi (physik instrumente) www.pi-usa.us mide technology corporation www.mide.com morgan technical ceramics www.morganelectroceramics.com electromagnetic energy harvesting another alternative ac source is an electromagnetic vibra- tion har vester in which a magnet vibrating inside a coil induces an ac voltage and current in the coil that can then be rectified and harvested by the LTC3330. the vibration could be ambient to the system or it could be caused by an impulse as in a spring loaded switch. solar energy harvesting the LTC3330 can harvest solar energy as the bridge recti - fier can be used to provide reverse protection for a solar panel . a solar cell produces current in proportion to the amount of light falling on it. figure 5 shows the relationship between current and voltage for a solar panel illuminated with several levels of light. the maximum power output occurs near the knee of each curve where the cell transi - tions from a constant current device to a constant voltage device. fortunately, the peak power point doesnt change much with illumination and an appropriate uvlo window can be selected so that the panel operates near the peak power point for a majority of light conditions. gnd LTC3330 piezo model v in c in ac1 3330 f04 i p sin(wt) c p figure 4. LTC3330 voltage doubler configuration tw o solar panels can be connected to the LTC3330, one from ac1 to ground and another from ac2 to ground. each panel could be aimed in a different direction to capture light from different angles or at different times of the day as the sun moves. the panels should be similar or the same so that the selected uvlo window is optimal for both panels. b at , v in , and v out capacitors the input capacitor for the buck- boost on the bat pin should be bypassed with at least 4.7 f to gnd. in cases where the series resistance of the battery is high, a larger capacitor may be desired to handle transients. a larger capacitor may also be necessary when operating close to 1.8 v with the higher i peak_ bb selections to prevent the battery voltage from falling below 1.8 v when the buck- boost is switching. the input capacitor to the buck on v in and the v out capaci- tor can vary widely and should be selected to optimize the use of an energy harvesting source depending on whether figure 5. typical solar panel characteristics v panel (v) 0 i panel (a) w panel (w) 500 400 300 200 100 0 1500 1200 900 600 300 0 2 3 4 5 3330 f05 6 1 sanyo 1815 solar panel 1800 lux 500 lux 200 lux 1000 lux panel voltage panel power 3330fa ltc 3330
21 for more information www.linear.com/LTC3330 applications storage of the harvested energy is needed at the input or the output. storing energy at the input takes advantage of the high input voltage as the energy stored in a capacitor increases with the square of its voltage. storage at the output may be necessary to handle load transients greater than the 100ma the buck can provide. the input or output capacitor should be sized to store enough energy to provide output power for the length of time required. if enough energy is stored so that the buck does not reach the uvlo falling threshold during a load transient then the battery current will always be zero. spacing load transients so that the average power required to service the application is less than or equal to the power available from the energy harvesting source will then greatly extend the life of the battery. the v in capacitor should be rated to withstand the highest voltage ever present at v in . the following equation can be used to size the input ca- pacitor to meet the power requirements of the output for the desired duration: p load t load = 1 2 c in v in 2 C v uvlofalling 2 ( ) v uvlofalling v in v shunt here is the average efficiency of the buck converter over the input voltage range and v in is the input voltage when the buck begins to switch. typically v in will be the uvlo rising threshold. this equation may overestimate the input capacitor necessary as it may be acceptable to allow the load current to deplete the output capacitor all the way to the lower pgood threshold. it also assumes that the input source charging has a negligible effect during this time. the duration for which the buck or buck-boost regulator sleeps depends on the load current and the size of the v out capacitor. the sleep time decreases as the load current increases and/or as the output capacitor decreases. the dc sleep hysteresis window is 6 mv for the 1.8 v output and scales linearly with the output voltage setting (12mv for the 3.6 v setting, etc.). ideally this means that the sleep time is determined by the following equation: t sleep = c out v dc_hys i load this is true for output capacitors on the order of 100f or larger, but as the output capacitor decreases towards 10f, delays in the internal sleep comparator along with the load current itself may result in the v out voltage slew- ing past the dc thresholds. this will lengthen the sleep time and increase v out ripple. a capacitor less than 10 f is not recommended as v out ripple could increase to an undesirable level. if transient load currents above 100ma are required then a larger capacitor should be used at the output. this capacitor will be continuously discharged during a load condition and the capacitor can be sized for an acceptable drop in v out : c out = v out + Cv out C ( ) i load Ci dc/dc t load here v out + is the value of v out when pgood goes high and v out C is the desired lower limit of v out . i dc/dc is the average current being delivered from either the buck converter or the buck-boost converter. the buck converter typically delivers 125 ma on average to the output as the inductor current is ramped up to 250 ma and down to zero. the current the buck-boost delivers depends on the mode of operation and the i peak_bb setting. in buck mode the deliverable current is i peak_bb/ 2. in buck-boost and boost modes the deliverable current also depends on the v in to v out ratio: buck-boost mode: i dc/dc = 3 4 i peak_bb v in v out boost mode: i dc/dc = 1 2 i peak_bb v in v out a standard surface mount ceramic capacitor can be used for c out , though some applications may be better suited to a low leakage aluminum electrolytic capacitor or a supercapacitor. these capacitors can be obtained from manufacturers such as vishay, illinois capacitor, avx , or cap-xx. 3330fa ltc 3330
22 for more information www.linear.com/LTC3330 applications supercapacitor balancer if supercapacitors are used at v out the onboard superca- pacitor balancer can be used to balance them with 10ma of balance current. a list of supercapacitor suppliers is provided in table 6. table 6. supercapacitor suppliers cap-xx www.cap-xx.com ness cap www.nesscap.com maxwell www.maxwell.com bussman www.cooperbussman.com avx www.avx.com illinios capacitor www.illcap.com tecate group www.tecategroup.com by seamlessly combining a battery source and an en- ergy harvesting source, the LTC3330 enables the use of supercapacitors in energy harvesting applications. the battery provides the initial current required to overcome the effects of the diffusion current when voltage is first applied to the supercapacitors. the energy harvesting source can then support the lower steady state leakage current and average load current. ldo capacitors the input to the low dropout regulator, ldo_in, should be bypassed with at least 4.7 f to gnd. if ldo_in is connected to v out the v out capacitor may adequately bypass the ldo input. if the board connection between ldo_in and v out is long then an additional 1 f bypass capacitor to gnd near the ldo_in pin may be required. the ldo_out capacitor should be at least 22 f to keep load step responses within 2% of regulation. a smaller capacitor may lead to worse transient response and/or instability whereas a higher capacitor will improve tran - sient response. cap, v in2 , and v in3 capacitors a 1 f or larger capacitor must be connected between v in and cap and a 4.7 f capacitor must be connected between v in2 and gnd. these capacitors hold up the internal rails during buck switching and compensate the internal rail generation circuits. in applications where the voltage at v in is limited to less than 6 v, the cap pin can be tied to gnd and the v in2 pin can be tied to v in as shown in figure 6. an optional 5.6 v zener diode can be connected to v in to clamp v in in this scenario. the leakage of the zener diode below its clamping voltage should be considered as it could be comparable to the quiescent current of the LTC3330. this circuit does not require the capacitors on v in2 and cap, saving two components and allowing for a lower voltage rating for the single v in capacitor. a 1 f or larger bypass capacitor must be connected from v in3 to ground. v in3 is an internal rail that is shared by both the buck and buck-boost. it is not intended for use as a system rail. it is used as a the logic high reference level for the ipk[2:0] and out [2:0] digital inputs. in the event that these pins are dynamically driven in the application, external inverters may be needed and they must use v in3 as a rail. however, care must be taken not to overload v in3 and the quiescent current of such logic should be kept minimal. the output resistance of the v in3 pin is typically 15k. figure 6. low voltage solar harvester with reduced component count (v in < 6v) LTC3330 3330 f06 ac1 v in cap v in2 ac2 sw v out scap bal ldo_in ldo2 ldo1 ldo0 ldo_en pgvout pg_ldo eh_on ldo_out 22h 1.8v v in3 1f 6.3v 33h li-ion uvlor = 4v uvlof = 3v ipeak_bb = 150ma 22f 6.3v 5.6v (optional) uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 swa swb gnd + 22f 6.3v solar panel + ? solar panel + ? 4.7f 6.3v 3330fa ltc 3330
23 for more information www.linear.com/LTC3330 applications inductor selection the buck is optimized to work with a 22 h inductor in typical applications. a larger inductor will benefit high voltage applications by increasing the on- time of the pmos switch and improving efficiency by reducing gate charge loss. choose an inductor with a dc current rating greater than 350 ma. the dcr of the inductor can have an impact on efficiency as it is a source of loss. tradeoffs between price, size, and dcr should be evaluated. the buck-boost is optimized to work with a minimum inductor of 22 h for the 250 ma i peak_bb setting. for the other seven i peak_bb settings the inductor value should increase proportionally as the i peak_ bb selection decreases. doing so maintains required minimum on- times of the four buck- boost switches. the minimum inductor values for the buck-boost for each i peak_bb setting are listed in table 3. larger inductors may increase efficiency. choose an inductor with an i sat rating at least 50% greater than the selected i peak value. table 7 lists several inductors that work well with both the buck and the buck-boost. table 7. recommended inductors for the LTC3330 part number l(h) manufacturer size (mm) (l w h) max idc (ma) max dcr () 744043102 lps5030-105ml lps4018-105ml lps3314-105ml b82442t1105k050 1000 w rth electronic coilcraft coilcraft coilcraft epcos 4.8 4.8 2.8 5.51 5.51 2.9 3.9 3.9 1.7 3.3 3.3 1.3 5.6 5 5 80 110 98 99 150 7 5.1 18 31 9.5 744043471 lps4018-474ml lps3314-474ml b82442t147k050 470 w rth electronic coilcraft coilcraft epcos 4.8 4.8 2.8 3.9 3.9 1.7 3.3 3.3 1.3 5.6 5 5 125 160 110 240 2.6 7.8 12 4.73 744042331 lps4018-334ml lps3314-334ml b82442t1334k050 330 w rth electronic coilcraft coilcraft epcos 4.8 4.8 1.8 3.9 3.9 1.7 3.3 3.3 1.3 5.6 5 5 130 190 110 280 4.5 5.9 9.3 3.29 744042221 lps4018-224ml lps3314-224ml b82442t1224k050 220 w rth electronic coilcraft coilcraft epcos 4.8 4.8 1.8 3.9 3.9 1.7 3.3 3.3 1.3 5.6 5 5 160 260 160 330 3.2 3.7 6 2.2 744031101 lps4018-104ml lps3314-104ml b82442t1104k050 100 w rth electronic coilcraft coilcraft epcos 3.8 3.8 1.65 3.9 3.9 1.7 3.3 3.3 1.3 5.6 5 5 180 360 230 510 2.4 1.4 2.75 0.99 744031470 lps4018-473ml lps3314-473ml b82442t1473k050 47 w rth electronic coilcraft coilcraft epcos 3.8 3.8 1.65 3.9 3.9 1.7 3.3 3.3 1.3 5.6 5 5 250 550 330 700 1 0.65 1.4 0.519 744031330 lps4018-333ml lps3314-333ml 1070bs-330ml b82442t1333k050 33 w rth electronic coilcraft coilcraft t oko epcos 3.8 3.8 1.65 3.9 3.9 1.7 3.3 3.3 1.3 3.2 3.2 2 5.6 5 5 320 640 380 230 840 0.66 0.42 0.92 0.61 0.36 744031220 lps5030-223ml lps4018-223ml lps3314-223ml 1070as-220m b82442t1223k050 22 w rth electronic coilcraft coilcraft coilcraft t oko epcos 3.8 3.8 1.65 5.51 5.51 2.9 3.9 3.9 1.7 3.3 3.3 1.3 3.2 3.2 2 5.6 5 5 360 750 800 450 410 1040 0.45 0.19 0.36 0.72 0.64 0.238 744029220 1069bs-220m 22 w rth electronic t oko 2.8 2.8 1.35 3.2 3.2 1.8 300 290 0.97 0.495 3330fa ltc 3330
24 for more information www.linear.com/LTC3330 applications summary of digital inputs and outputs there are 14 digital pin-strapped logic inputs to the LTC3330 and three digital logic outputs. these and the rails they are referenced to are summarized in table 8. table 8. digital pin summary input pin logic high level uv[3:0] v in2 ipk[2:0] v in3 out[2:0] v in3 ldo[2:0] ldo_in ldo_en ldo_in up to 6v output pin logic high level pgvout max ( bat , v in2 , v out ) pgldo max ( bat , v in2 , v out ) eh_on v in3 LTC3330 system solutions the LTC3330 can be paired with other linear technology low quiescent current integrated circuits to form a multirail sys - tem. figure 7 shows an LTC3330 powering an ltc3388-3 from its 5 v output. the ltc3388-3, an 800 na buck converter, is configured here to produce a negative 5v rail by tying the v out pin to ground and tying its gnd pin to the regulated C5 v output. the result is a 5 v energy harvesting power supply with battery backup. figure 7. dual 5v power supply with a 3.3v ldo output LTC3330 3330 f07 ac1 v in cap v in2 ac2 sw v out scap bal ldo_in ldo2 ldo1 ldo0 ldo_en pgvout pg_ldo eh_on ldo_out 22h v in3 1f 6.3v 22h li-ion uvlor = 12v** uvlof = 11v ipeak_bb = 250ma 22f 25v 1f, 6.3v 4.7f, 6.3v uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 swa swb gnd + 22f 6.3v 3.3v *exposed pad must be electrically isolated from system ground and connected to the ?5v rail **for peak power transfer, center the uvlo window at half the rectified open circuit voltage of the piezo 4.7f 6.3v mide v25w v in pgood cap v in2 sw en v out ltc3388-3* gnd d1 d0 stby 4.7f 6.3v 1f, 6.3v 22f 6.3v 5v ?5v 2.2f 10v 22f 6.3v 22h 3330fa ltc 3330
25 for more information www.linear.com/LTC3330 when paired with the 550 na ltc4071 shunt battery charger with low battery disconnect the LTC3330 can charge a bat- tery from an energy harvesting source as shown in figure 8. a batter y is connected to the b at pin of the ltc4071. if the battery voltage drops below a selected level the battery will be disconnected and protected from further discharge. a charging resistor is connected from v in of the LTC3330 to v cc of the ltc4071 to create a charging path. v cc is then the input to the LTC3330 buck-boost at the bat pin. the charging resistor should be sized in accordance with the available energy from the energy harvesting source to allow the v in pin voltage of the LTC3330 to reach the applications figure 8. energy harvesting battery charger with low battery disconnect uvlo rising threshold and prioritize powering the output at v out . higher efficiency battery powered buck if the battery voltage will always be higher than the regu- lated output of the LTC3330 then the battery powered buck-boost will always run in buck mode. in this case the inductor that is usually placed between swa and swb can go directly to v out from swa , bypassing internal switch m 4 of the buck-boost (figure 9). this will reduce conduction losses in the converter and improve the ef- ficiency at higher loads. LTC3330 3330 f08 ac1 v in cap v in2 ac2 sw 3.3v v out scap bal ldo_in ldo2 ldo1 ldo0 ldo_en pgvout pg_ldo eh_on ldo_out 22h v in3 1f 6.3v 220h li-ion uvlor = 12v* uvlof = 11v ipeak_bb = 25ma 22f 25v 330k 1f, 6.3v 4.7f, 6.3v uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 swa swb gnd + 22f 6.3v 1.8v 4.7f 6.3v mide v25w 22f 6.3v bat adj ntc ltc4071 gnd v cc lbsel *for peak power transfer, center the uvlo window at half the rectified open circuit voltage of the piezo 3330fa ltc 3330
26 for more information www.linear.com/LTC3330 applications figure 9. higher efficiency battery powered buck regulator efficiency comparison between normal buck-boost and bypassed swb configuration bat (v) efficiency (%) 3330 f09b 100 95 90 85 80 75 2.5 3 3.5 4 4.5 5.55 v out = 1.8v, bypass swb v out = 1.8v, include swb v out = 3.3v, bypass swb v out = 3.3v, include swb l = 22h, dcr = 0.36, 100ma load LTC3330 3330 f09a ac1 swb swa v in cap v in2 ac2 sw 1.8v v out scap bal ldo_in ldo2 ldo1 ldo0 ldo_en pgvout pg_ldo eh_on ldo_out 22h v in3 1f 6.3v uvlor = 14v* uvlof = 13v ipeak_bb = 250ma 22f 25v 1f, 6.3v 4.7f, 6.3v uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 gnd 22f 6.3v 1.5v 4.7f 6.3v mide v25w 22f 6.3v 22h li-ion + *for peak power transfer, center the uvlo window at half the rectified open circuit voltage of the piezo 3330fa ltc 3330
27 for more information www.linear.com/LTC3330 applications alternative power sources the LTC3330 can accommodate a wide variety of input sources. figure 10 shows the LTC3330 internal bridge rectifier connected to a 120 v rms ac line in series with four 150 k current limiting resistors. this produces a peak current of 250 a with the LTC3330 shunt holding v in at 20 v. this current may be increased by reducing the resistor values since the shunt can sink 25 ma and the bridge is rated for 50 ma. an optional external zener diode ( shown) may be required if the current exceeds 25ma. a transformer may also be used to step down the voltage and reduce the power loss in the current limiting resistors. this is a high voltage application and minimum spacing between the line, neutral, and any high voltage components should be maintained per the applicable ul specification. for general off-line applications refer to ul regulation 1012. figure 11 shows an application where copper panels are placed near a standard fluorescent room light to capaci - tively har vest energy from the electric field around the light. the frequency of the emission will be double the line frequency for magnetic ballasts but could be higher if the light uses electronic ballast. the peak ac voltage and the total available energy will scale with the size of the panels used and with the proximity of the panels to the electric field of the light. using eh_on to program v out the eh_ on output indicates whether the energy harvesting input or the battery is powering the output. the application on the last page of this data sheet shows the eh_on output tied to the out2 input. when eh_on is low the output is programmed to 2.5 v and the battery powers the output. when energy harvesting is available eh_on is high and the output is programmed to 3.6 v allowing for increased storage of harvested energy. if energy harvesting goes away, the output is again programmed to 2.5 v and the buck-boost converter will be in sleep until the output is discharged to the wake-up threshold. if the energy stored at 3.6 v is enough to ride through a temporary loss of energy harvesting then the only drain on the battery will be the quiescent current in sleep. 3330fa ltc 3330
28 for more information www.linear.com/LTC3330 applications dangerous and lethal potentials are present in offline circuits! before proceeding any further, the reader is warned that caution must be used in the construction, testing and use of offline circuits. extreme caution must be used in working with and making connections to these circuits. repeat: offline circuits contain dangerous, ac line- connected high voltage potentials, use caution. all testing performed on an offline circuit must be done with an isolation transformer connected between the offline circuit s input and the ac line. users and constructors of offline circuits must observe this precaution when connecting test equipment to the circuit to avoid electric shock. repeat: an isolation transformer must be connected between the circuit input and the ac line if any test equipment is to be connected. figure 10. ac line powered 5v ups LTC3330 3330 f10 ac1 v in cap v in2 ac2 150k 150k 120vac 60hz sw v out scap bal ldo_in ldo2 ldo1 ldo0 ldo_en pgvout pg_ldo eh_on ldo_out v in3 1f 6.3v 22h uvlor = 18v uvlof = 5v ipeak_bb = 250ma 22f 25v 1f, 6.3v 4.7f, 6.3v uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 swa swb gnd 2.5v 4.7f 6.3v 22f 6.3v 18v (optional) 5v 10mf 2.7v 10mf 2.7v 10f 6.3v 22h 150k 150k danger high voltage li-ion + 3330fa ltc 3330
29 for more information www.linear.com/LTC3330 figure 11. electric field energy harvester applications LTC3330 3330 f11 ac1 v in cap v in2 ac2 copper panel (12" 24") sw v out scap bal ldo_in ldo2 ldo1 ldo0 ldo_en pgvout pg_ldo eh_on ldo_out v in3 1f 6.3v 1000h uvlor = 14v uvlof = 5v ipeak_bb = 5ma 22f 25v 1f, 6.3v 4.7f, 6.3v uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 swa swb gnd 3.3v 4.7f 6.3v 22f 6.3v 4.5v 220mf 2.7v 220mf 2.7v 10f 6.3v 22h li-ion + copper panel (12" 24") 3330fa ltc 3330
30 for more information www.linear.com/LTC3330 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 3330fa ltc 3330
31 for more information www.linear.com/LTC3330 revision history rev date description page number a 03/14 clarified typical application clarified absolute maximum ratings table clarified electrical characteristics table clarified graphs clarified figure 1 1 2 3, 4, 5 6, 9, 10 16 3330fa ltc 3330
32 for more information www.linear.com/LTC3330 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2013 lt 0314 rev a ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC3330 ups system for wireless mesh networks with output supercapacitor energy storage LTC3330 3330 ta02 ac1 v in cap v in2 ac2 sw v out scap bal ldo_in ldo2 ldo1 ldo0 ldo_en pgvout pg_ldo eh_on ldo_out v in3 1f 6.3v 22h li-socl 2 uvlor = 8v* uvlof = 7v ipeak_bb = 250ma 22f 25v 1f, 6.3v 4.7f, 6.3v uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 swa swb gnd + 4.7f 6.3v mide v25w linear technology dc9003a-ab dust mote for wireless mesh networks pgood ehorbat t x v supply gnd v out = 3.6v for eh_on = 1 v out = 2.5v for eh_on = 0 1f 2.7v 1f 2.7v 10f 6.3v 22h *for peak power transfer, center the uvlo window at half the rectified open circuit voltage of the piezo related parts typical application part number description comments lt1389 nanopower precision shunt voltage reference v ref : 1.25v, 2.25v, 4.096v; i q = 800na; i sd < 1a; so-8 package ltc1540 nanopower comparator with reference v in : 2v to 11v; i q = 0.3a; i sd < 1a; 3mm 3mm dfn-8 package lt3009 3a i q , 20ma low dropout linear regulator v in : 1.6v to 20v; v out(min) : 0.6v, fixed 1.2v to 5v; i q = 3a; i sd < 1a; sc-70-8, 2mm 2mm dfn-8 packages ltc 3105 400ma step-up converter with mppc and 250mv start-up v in : 0.2v to 5v; v out(min) : max 5.25v; i q = 22a; i sd < 1a; 3mm 3mm dfn-10, msop-12 package ltc3108 ultralow voltage step-up converter and power manager v in : 0.02v to 1v; v out(min) : fixed 2.35v to 5v; i q = 7a; i sd < 1a; tssop-16, 3mm 4mm dfn-12 packages ltc 3109 auto-polarity, ultralow v oltage step-up converter and power manager v in : 0.03v to 1v; v out(min) : fixed 2.35v to 5v; i q = 7a; i sd < 1a; ssop-20, 4mm 4mm qfn-20 packages ltc 3388-1/ ltc3388-3 20v, 50ma high efficiency nanopower step-down regulator v in : 2.7v to 20v; v out(min) : fixed 1.1v to 5.5v; i q = 720na; i sd = 400na; msop-10, 3mm 3mm dfn-10 packages ltc 3588-1/ ltc3588-2 piezoelectric energy har vesting power supply with up to 100ma of output current v in : 2.7v to 20v; v out(min) : fixed 1.8v to 5v; i q = 950na; i sd = 450na; msop-10, 3mm 3mm dfn-10 packages ltc 4070 50ma micropower shunt li-ion charge v out(min) : 4v, 4.1v, 4.2v; i q = 450na; i sd = 45na; msop-8, 2mm 3mm dfn-8 packages ltc4071 50ma micropower shunt li-ion charge with powerpath? control v out(min) : 4v, 4.1v, 4.2v; i q = 450na; i sd = 45na; msop-8, 2mm 3mm dfn-8 packages ltc3129/ ltc3129-1 micropower 200ma synchronous buck-boost dc/dc converter v in : 2.42v to 15v; v out(min) : 1.4v to 15v; i q = 1.3a; i sd = 10na; msop-16e, 3mm 3mm qfn-16 packages 3330fa ltc 3330

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